VMETRO Introduces Serial FPDP IP Core Support for Xilinx FPGAs
HOUSTON—(BUSINESS WIRE)—Aug. 17, 2005—
VMETRO announces the immediate availability of a Serial
FPDP IP core for use on its range of Xilinx Virtex-II Pro FPGA
products. The combination of VMETRO hardware, Serial FPDP IP, and user
programmable FPGAs enables high-performance, highly integrated
solutions for a wide range of applications including signal
processing, high speed data recorders, real-time imaging, and test
systems relying on Serial FPDP I/O.
The SFPDP IP core is fully compliant with ANSI 17.1-2003 (Serial
FPDP) and provides easy creation of point-to-point data links with a
choice of 1.0625Gbps, 2.125Gbps, and 2.5Gbps FPGA RocketIO connections
when using suitable host FPGA cards. Using fiber optic transceivers,
these data links can range from just a few meters to more than 10km.
All serial FPDP operating modes are supported, including simple
unidirectional links, bi-directional links with dataflow control, copy
mode, and copy-loop mode. These modes offer great flexibility in data
transfer and allow for multiple end-points which is especially useful
when simultaneously recording and processing raw data.
The IP core occupies only a small logic resource footprint in an
FPGA; each Serial FPDP interface occupies around 1% of a Virtex II Pro
version XC2VP70. This enables most of the FPGA to be used for user IP
even if several Serial FPDP interfaces are required on a single
device.
"We are seeing customers that have a need for front-end processing
of their Serial FPDP data, such as collating data from several Serial
FPDP links into a single data stream," says Dave Barker, Vice
President of Business Development for Processing Solutions at VMETRO.
"This offering from VMETRO allows customers to integrate within a
single FPGA their front-end processing logic with a fully compliant
Serial FPDP core. For instance, customers can use a VMETRO PMC-FPGA03F
Virtex-II Pro PMC to receive and perform the front-end processing of
Serial FPDP data before sending it to a host CPU node for back-end
processing."
The Serial FPDP IP core is provided in an EDIF format with
obfuscated source for simulation. The core can be implemented on
VMETRO's FPGA products such as the PMC-FPGA03/03F, the VPF1, and the
3CPF1 lines of air cooled and rugged/conduction cooled products. In
addition, customers can implement the core into their own FPGA
hardware such as a sensor that will be communicating via Serial FPDP
to a VMETRO processing or recording system. Subject to licensing
conditions, the core can also be used on non-VMETRO based FPGA
products.
The Serial FPDP IP core is priced from US$6,000.
About VMETRO
VMETRO offers products and services that enable clients to build
superior high-end digital processing, recording and sensor I/O systems
for their customers, on time! The products are based on open standards
like VXS, VME, PCI, cPCI and RACEway. Founded in 1986 in Oslo, Norway,
and in the US since 1987, VMETRO is the world's largest manufacturer
of bus analyzers for standard buses such as VME and PCI. VMETRO also
offers an extensive line of high-performance signal processing
solutions, real-time data recorders, PMC I/O controllers and modules
for real-time data processing, acquisition and networking. VMETRO
merged with Transtech DSP Ltd (High Wycombe, UK) October 1, 2004,
adding a powerful range of signal processing products to the VMETRO
product range. VMETRO is traded on the Oslo Stock Exchange (OSE:VME).
For more information, please visit www.vmetro.com
Contact:
VMETRO
In Europe/Asia:
Jeremy Banks, +44 (0) 1494 476000
E-mail: Email Contact
or
In USA/Canada:
Dave Barker, 281-584 0728
E-mail: Email Contact
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